Serial Audio Data Interface : Multi-channel & HBR Audio Interface
The IP supports off-chip audio codec interface with 3-wired serial communication(I2S). Additionally, MCLK(Audio Master Clock) is supported and can be used if necessary. This IP supports an audio sampling frequency of 192 kHz and supports up to 32 bits of audio data bit width. And, it supports master and slave clock mod..
3.75GHz Clock generator with bandwidth shifting algorithm
The power noise caused near to the PLL bandwidth considerably affects the PLL performance due to gain peaking. Therefore, it is strongly recommended to use an adaptive bandwidth PLL to switch bandwidth to lower the gain peaking under noisy environment. The proposed PLL checks whether the power noise frequency is near t..
4GHz DLL Based Clock Generator
A DLL Based Clokc Generator that operates at 2GHz is introduced in this paper. The proposed method has a simple architecture with VCDL and combiner. The reference frequency is 500MHz. The Combiner can make maximum 4 times of reference clock freqency.
Additionaly, when the clock is changed, the output clock has dithe..
2.7GHz 5000ppm Spread spectrum clock generator
This is a 2.7GHz 5000ppm Spread Spectrum Clock Generator (SSCG) which is designed for DisplayPort version 1.2. An Electro-Magnetic Interference (EMI) can be reduced effectively in high-speed interface communications. In this SSCG, fundamentally fractional-N PLL is implemented for this EMI reduction effect. A designed S..
Wake Up Receiver for 5.8GHz
This IP consists of envelope detector, amplifier, comparator, and delay-based BPF (Band Pass Filter). The RF input passes through RMS detector. If there is wake-up signal, the detector detects the envelope of the signal, and gives the detected signal to the following ASK demodulator block.
The envelope signal detect..