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Interface > MHL > (Type) PHY > (Sub-type) RX
  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 3/850 IP Cores
    • 기업 IP
    • N
    • M
    • T

    4-port HDMI 1.4b/MHL2.0 receiver PHY&Link

    This IP is a 4 - port PHY and Link IP. It is composed of two major blocks. This IP is a PHY IP which receives HDMI and MHL serial data and transform into parallel data. This is a LINK IP which converts received parallel data into video format. This IP is capable of receiving 4 - HDMI or MHL ports. The selected HDMI/MH..

    KC553H0692 | 2015-06-30

    • 기업 IP
    • N
    • M
    • T

    MHL 2.1 RX(Receiver) PHY

    This IP implemented MHL version 2.1 receiver PHY(Physical layer Analog front end) with TSMC 65nm process and was proven with silicon ASIC chip. This receives MHL signal from MHL cable and recovers data and outputs the data for MHL Link layer processing. MHL(Mobile High-Definition Link) is an industry standard for a m..

    KC131H0477 | 2013-12-19

    • 기업 IP
    • N
    • M
    • T

    4-port HDMI 1.4b/MHL2.0 receiver PHY&Link

    This IP is a 4 - port PHY and Link IP. It is composed of two major blocks. This IP is a PHY IP which receives HDMI and MHL serial data and transform into parallel data. This is a LINK IP which converts received parallel data into video format. This IP is capable of receiving 4 - HDMI or MHL ports. The selected HDMI/MH..

    KC251H0426 | 2013-10-17