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total: 1/847 IP Cores
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    LPDDR Memory controller

    The LPDDR SDRAM memory controller with the AHB interface is used to control LPDDR SDRAM devices. The LPDDR memory controller has AHB interface 128bit data width and controls dual x32 LPDDR SDRAM devices. All access timing parameter such as CAS latency, RAS-to-CAS delay, Refresh interval, etc., are programmable to suppo..

    KU195S0634 | 2015-04-04