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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 8/850 IP Cores
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    DisplayPort / eDP RX IP

    The eDP RX IP supports DisplayPort ver. 1.3 and eDP ver 1.4 that are presented by VESA (Video Electronics Standards Association) standards. The IP consists of two major blocks which are RX physical layer and link layer. The transmitted DP/eDP data signal from source is converted to digital signal by CDR (clock and data..

    KC563H0880 | 2017-04-18

    • 기업 IP
    • N
    • T
    • P

    DisplayPort 1.2 RX Link Layer

    DisplayPort is the latest digital audio/video interface standard presented by VESA (Video Electronics Standards Assiciation). It unifies and standardizes individually different types of interfaces in/outside display system so that computers, monitors and home theater system (TV, audio) can be linked with display system..

    KC133S0677 | 2015-06-11

    • 대학·연구소 IP
    • T

    DisplayPort v1.2a Receiver PHY

    A receiver that supports the DisplayPort version 1.2a standard of the Video Electronics Standards Association (VESA) is introduced. This receiver consists of an adaptive equalizer, referenceless CDR, and built in self-test (BIST) block. A simple architecture of the equalizer compensates the channel adaptively. The refe..

    KU064H0587 | 2014-11-11

    • T

    DisplayPort v1.2 FAUX Sink Rx

    This architecture is for one of the DisplayPort channel. This FAUX channel is referenceless and half-duplex bi-directional channel. As CMOS technology process is scaled down, the digital operation abilities of integrated circuits increase. This trend leads to growing demands of digital integrated circuits which are eas..

    KS064H0287 | 2013-01-02

    • T

    DisplayPort v.1.2 FAUX sink transmitter

    DisplayPort v.1.2 FAUX sink transmitter circuit is fabricated in a 0.11 um CMOS technology. Proposed transmitter consists of 10:1 serializer, phase locked loop for 720MHz clock, output driver. The reference clock comes from sink clock and data recovery (CDR) circuit because sink side does not have reference clock. The ..

    KS064H0269 | 2012-11-07