DT-MIPI D-PHY RX
This DPHY-RX is a high-frequency low-power, low-cost, source- synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, The High-Speed signals have a low voltage swing, while Low-Power signals have lar..
Low power 8Gbps SerDes
SerDes with 8.0Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its function w..
HDMI 2.1 Transmitter
SPHTG2 provides a complete single-link HDMI transmitter function complies with HDMI specification version 2.1. It consists of two modules, a physical layer and a link module. The PHY is upper compatible with DVI transmitter and implemented as a hard IP based on an Samsung 8nm LPP process, while the link module is imple..
SPLVRS04 is Alpha Solutions’ low-voltage differential signaling (LVDS) receiver. It converts four LVDS data streams back into 28 bits of data. At a transmit clock frequency of 240 MHz five LVDS data channels at the speed of 1.68 Gbps per LVDS data channel conveys up to 24 bits RGB data at 240 MHz pixel rate.
Cascadable USI-T Receiver/Transmitter
Cascadable USI-T Receiver/Transmitter IP fully compliant to USI-T standard. The IP incorperates PLL for hgh speed clock generation, 2 USI-T RX lanes and 2 USI-T TX lanes for data transmittion. Each data lane and can transmit date rate of 1Gbps ~ 2Gbps. The IP can be cascades upto 30 ICs. With cascade function, IP is su..