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DisplayPort v1.2 FAUX Sink Rx
This architecture is for one of the DisplayPort channel. This FAUX channel is referenceless and half-duplex bi-directional channel. As CMOS technology process is scaled down, the digital operation abilities of integrated circuits increase. This trend leads to growing demands of digital integrated circuits which are eas..
KS064H0287 | 2013-01-02
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DisplayPort v.1.2 FAUX sink transmitter
DisplayPort v.1.2 FAUX sink transmitter circuit is fabricated in a 0.11 um CMOS technology. Proposed transmitter consists of 10:1 serializer, phase locked loop for 720MHz clock, output driver. The reference clock comes from sink clock and data recovery (CDR) circuit because sink side does not have reference clock. The ..
KS064H0269 | 2012-11-07
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DisplayPort v1.2 FAUX Source Rx
This architecture is for one of the DisplayPort channel. This FAUX channel is referenceless and half-duplex bi-directional channel. A CDR in source receiver is the DLL based CDR. The source device has the reference clock and the transmitter already makes the 720-MHz clock. By using relatively clean clock from PLL, smal..
KS064S0267 | 2012-11-07
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DisplayPort v.1.2 FAUX Source Transmitter
DisplayPort v.1.2 FAUX sink transmitter circuit is fabricated in a 0.11 um CMOS technology. Proposed transmitter consists of 10:1 serializer, phase locked loop (PLL) for 720MHz clock, output driver. The reference clock comes from sink clock and data recovery (CDR) circuit because sink side does not have reference clock..
KS064S0265 | 2012-11-07
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Transceiver for DisplayPort v1.1a
The single-loop referenceless CDR with WPFD has advantages in terms of power and area over conventional dual-loop clock and data recovery schemes. In addition, the proposed CDR is designed to operate with half-rate clock, for further power reduction and easier design. The recovered clock jitters are 13.2psp-p and 1.57p..
KU064H0170 | 2011-07-01