AHB Interconnect Matrix
AHB interconnect matrix provides multiple channels for multiple master platforms. The configuration of the network is parameterized so that the number of masters and slaves can be determined by changing parameters
AHB interface for CY7C1354B (256K x 36 SRAM)
CY7C1354B is 256k x 36 synchronous pipelined burst SRAM(Static random access memory) with No Bus Latency(NoBL) logic. It is designed to support unlimited true back-to-back Read/Write operations with no wait states. This interface logic is design for CY7C1354B to support single/burst transmission on AHB bus. The interfa..
AHB interface for Xilinx DDR1 memory interface generator(MIG)
This interface is design for DDR1 SODIMM socket. Xilinx DDR1 interface is generated from memory interface generator of Xilinx. The user-application-interface of DDR1 do not support AHB. We design the AHB interface for Xilinx DDR1 memory interface generator.