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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 24/847 IP Cores
    • 기업 IP
    • N
    • M
    • T

    PLL 3G

    The PLL 3G IP is Clock Generator PLL that Widely programmable fractional-N delta sigma frequency synthesizer. PLL 3G uses only RVT device to provide a clock with a maximum frequency of 3.5GHz. It contains a 1-64 divider at the reference clock input, a 16-2000(Integer Mode) divider in the internal feedback path, and ..

    KC639H1109 | 2021-11-10

    • 기업 IP
    • M
    • T

    PLL 60to300MHz

    PLLs have been developed as phase locked loops in a variety of applications. The PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N “FOUT = FIN/M*N”

    KC022H1007 | 2019-11-19

    • 기업 IP
    • M

    PLL 60to300MHz

    The PLL have been developed as phase locked loops in a variety of applications. This PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N “FOUT = FIN/M*N”

    KC022H0959 | 2018-11-26

    • 대학·연구소 IP
    • P

    Analog PLL

    This 100MHz&125MHz PLL allows implementation of integer-N frequency synthesizers when used with an internal loop filter and external reference frequency. It is designed in 130nm BCDMOS technology for automotive applications and consists of phase and frequency detector(PFD), charge pump(CP), analog loop filter, voltage..

    KU335H0836 | 2016-10-14

    • 대학·연구소 IP
    • T

    All Digital Phase Locked Loop with Single stage TDC

    This work 1.45-2.9 GHz all digital phase locked loop(ADPLL) with combination of Bang-Bang Phase Frequency Detector(BBPFD) and single stage time-to-digital converter(TDC). Single stage TDC was designed in Vernier type used for fine control to reduce output jitter and provide controllable larger gain than merely using co..

    KU085H0826 | 2016-09-13