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All-digital Fractional-ratio Frequency Multiplying Delay-Locked Loop
An all-digital frequency multiplying delay-locked loop (FMDLL) that provides both programmable fractional-ratio clock multiplication and zero-skew capability for high performance clocking applications is presented. In contrast to conventional MDLLs that can generate only integer clock multiplication, the proposed clock..
KU386H0608 | 2014-12-01
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Multi-phase Fractional-ratio Frequency Multiplying Delay-Locked Loop
A multi-phase frequency multiplying delay-locked loop (FMDLL) that provides both programmable fractional-ratio clock multiplication and zero-skew capability for high performance clocking applications is presented. The proposed multi-phase FMDLL provides equally spaced 8-phase clock outputs.
Implemented in a 65nm 1.0-V..
KU386H0607 | 2014-12-01
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Anti-harmonic Fractional-ratio Frequency Multiplying Delay-Locked Loop
A reset-free anti-harmonic fast-lock frequency multiplying delay-locked loop (FMDLL) that provides both programmable fractional-ratio clock multiplication and zero-skew capability for high performance clocking applications is presented. The proposed FMDLL removes harmonic locking problems by utilizing a simple harmonic..
KU386H0606 | 2014-12-01
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A single capacitor loop filter PLL
This IP is a novel architecture of PLL which can reduce the size of loop filter components. A single capacitor loop filter PLL can be integrated into a chip. The inclusion of a one more negative feedback loop into a conventioanl PLL enables the PLL work very stably. It makes the conventional PLL with a one more negativ..
KU245S0517 | 2014-06-11
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6Gbps EDC based CDR
A 6Gb/s Transceiver with Electronic Dispersion Compensator
for Directly Modulated Distributed-Feedback Lasers
KC512H0512 | 2014-05-13