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Pipelined Parallel Huffman Decoder for GZIP
This Huffman decoder is designed by deflate/inflate algorithm. However, This IP need additional memory for decoding. This Huffman decoder output decoded symbols or LZ77 encoded code.
KU384S0901 | 2017-05-20
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Parallel Huffman Decoder for GZIP
This Huffman decoder is designed by deflate algorithm. However, This IP need additional memory for decoding. This Huffman decoder output decoded symbols or LZ77 encoded code
KU384S0891 | 2017-05-18
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Digital Signal Processing (DSP) IP for High Performance Hearing-aid SoC
The designed DSP IP can be used for a platform considers both flexibility and high performance in maintaining low power consumption by using ASIC accelerators. The designed DSP IP is composed of several ASIC accelerators. The accelerators are implemented as ASIC version, which are analysis/synthesis filter bank (A/SFB)..
KU360S0850 | 2017-02-07
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Edge detetive System fo IPS
in order to implement the IP of edge detection algorithm for surveillance in image using the camera in CCTV or vehicle black box, we designed pre-processing step that is the edge extraction algorithm. First, after input image converts into the input signals of R, G, and B, three inputs are combined, and converted to gr..
KU429S0759 | 2016-04-06
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Digital Audio AMP
This IP is a intergrated Class-D Digital Audio Amplifier which supports 2.1 Channel Stereo Audio. It includes I2C/I2S Serial Interface, Sigma-Delta Modulator, PWM Modulator and two Low Jitter PLLs.
KC014S0627 | 2015-02-25